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Commit 4edc51ec authored by Santiago Ospina's avatar Santiago Ospina
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Redistribution of the memory RAM layout while compiling. This order of...


Redistribution of the memory RAM layout while compiling. This order of compilation allows to use higher number of processors while compiling without filling the memory (of the generated code) as fast as before.
Signed-off-by: default avatarSantiago Ospina <saospina@hugo.iwr.uni-heidelberg.de>
parent f3feacd5
add_library(dorie-impl STATIC
sim_ug_2_1.cc
sim_ug_2_2.cc
sim_ug_2_3.cc
sim_ug_3_1.cc
sim_ug_3_2.cc
sim_ug_3_3.cc
sim_yasp_2_1.cc
sim_yasp_2_2.cc
sim_ug_2_1.cc
sim_yasp_2_3.cc
sim_yasp_3_1.cc
sim_ug_2_2.cc
sim_yasp_3_2.cc
sim_yasp_3_3.cc)
\ No newline at end of file
sim_yasp_3_3.cc
sim_ug_2_3.cc
sim_ug_3_1.cc
sim_ug_3_2.cc
sim_ug_3_3.cc)
\ No newline at end of file
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